1. Field of the Invention
The present invention relates to an output circuit for a semiconductor integrated circuit using digital signals.
2. Description of the Related Art
Recently, the operation speed of semiconductor integrated circuits such as memories is getting faster and faster. Therefore, high speed pulse signals which are output from the output stage tend to suffer from a high range distortion such as an undershoot and/or overshoot. When the undershoot and/or overshoot takes place, the voltage on the power supply voltage line and the ground line fluctuates excessively and thereby causes troubles such as noise and malfunction.
As shown in FIG. 1, an output circuit known to the inventor has an inverter 14 which consists of a PMOS (P-channel type Oxide Semiconductor) transistor 10 and an NMOS (N-channel type Oxide Semiconductor) transistor 12, an inverter 20 which consists of a PMOS transistor 16 and NMOS transistor 18, an drive PMOS transistor 22, a drive NMOS transistor 24, input terminals 26 and 28, power supply voltage terminals 30 and 32, and a output terminal 34.
The two inverters 14 and 20 are connected to the MOS transistors 22 and 24, respectively. A power is supplied to the source of the MOS transistor 22, the source of the MOS transistor 24 being grounded. The connecting point between the MOS transistors 22 and 24 is connected to the output terminal 34. When digital signals having the same phase with each other are sent to the input terminals 26 and 28 respectively, a signal having the same phase as the input signals is output from the output terminal 34.
However, in the output circuit shown in FIG. 1, when input signals to the two MOS transistors 22 and 24 changes from H (high) level to L (low) level or vice versa, the undershoot and/or overshoot takes place.
To remove such the undershoot and/or overshoot, the output circuit is structured as shown in FIG. 2. In other words, it is necessary to place resistors 36 and 38 between the inverters 14 and 20 and between the MOS transistors 22 and 24, respectively. The resistors 36 and 38 allow the through rate of signals from the input terminals 26 and 28 to be decreased and thereby preventing the voltage which is output from the output terminal 34 from abruptly changing.
However, in case that the undershoot and/or overshoot is suppressed with such resistors, since the output signal is delayed, it is difficult to increase the speed of the signal.